NoICE for the 68HC12 may be used with
Most HC12 variants include two or more hardware breakpoints, which NoICE can use to set breakpoints on code in Flash or EPROM memory.
In addition to this document, you may wish to read the NoICE HC12 Tutorial at https://www.noicedebugger.com/tour. It contains step-by-step examples of configuring and using NoICE for HC12.
There are many flavors of 68HC12, and Motorola/Freescale comes out with more all the time. The following table shows the 68HC12 variants currently supported by NoICE. Our documentation may lag our actual support. The definitive list of chips supported by any version of NoICE is the list shown in the Target Communications dialog, which is derived from the files config/NoICE12_targets.ini.
We have carefully constructed the support files based on the latest Motorola/Freescale documentation, but we do not have the resources to verify NoICE with all of these targets. If you have any problems, questions about a specific target, or need support for a target not listed here, please Contact us.
| Processor Variant | Comments |
|---|---|
| Generic HC12 | No hardware breakpoint, no Flash. Just about any system with code in RAM. Not usually the one you want to use. |
| MC9S12A64 | Has two 24-bit hardware breakpoints |
| MC9S12A128 | Has two 24-bit hardware breakpoints |
| MC9S12A256 | Has two 24-bit hardware breakpoints. Some masks have BDM-versus-PLL bug (MUCTS00436). NoICE sets CLKSW as a work-around |
| MC9S12A512 | Has two 24-bit hardware breakpoints |
| MC9S12B128 | Has two 24-bit hardware breakpoints |
| MC9S12C32 | Has three 24-bit hardware breakpoints. Tested on Technological Arts MicroCORE12. |
| MC9S12C64 | Has three 24-bit hardware breakpoints. Some chips have incorrect PARTID: they are actually C128 parts, labelled as C64. |
| MC9S12C128 | Has three 24-bit hardware breakpoints. |
| MC9S12Dx64 (DG, DP, DT, etc.) |
Has two 24-bit hardware breakpoints |
| MC9S12Dx128 (DG, DP, DT, etc.) |
Has two 24-bit hardware breakpoints |
| MC9S12Dx256 (DG, DP, DT, etc.) |
Has two 24-bit hardware breakpoints. Some masks have BDM-versus-PLL bug (MUCTS00436). NoICE sets CLKSW as a work-around. Tested on Elektronikladen HCS12 T-board and Technological Arts Adapt9S12DP256. |
| MC9S12Dx512 (DG, DP, DT, etc.) |
Has two 24-bit hardware breakpoints |
| MC9S12E64 | Has three 24-bit hardware breakpoints. Some chips have incorrect PARTID: they are actually E128 parts, labelled as E64. |
| MC9S12E128 | Has three 24-bit hardware breakpoints. Tested on Technological Arts Adapt9S12E128. |
| MC9S12E256 | Has three 24-bit hardware breakpoints. |
| MC9S12H256 | Has two 24-bit hardware breakpoints. Some masks have BDM-versus-PLL bug (MUCTS00436). NoICE sets CLKSW as a work-around |
| MC9S12HZ256 | Has two 24-bit hardware breakpoints. Some masks have BDM-versus-PLL bug (MUCTS00436). NoICE sets CLKSW as a work-around |
| MC9S12KG128 | Has three 24-bit hardware breakpoints. |
| MC9S12KT256 | Has three 24-bit hardware breakpoints. |
| MC9S12NE64 | Has three 24-bit hardware breakpoints. |
| MC9S12UF32 | Has two 24-bit hardware breakpoints. |
| MC9S12XA128, 256, 512 | Has three 24-bit hardware breakpoints. |
| MC9S12XB128, 256 | Has three 24-bit hardware breakpoints. |
| MC9S12XD128, 256 | Has three 24-bit hardware breakpoints. |
| MC9S12XDG128 | Has three 24-bit hardware breakpoints. |
| MC9S12XDP512 | Has three 24-bit hardware breakpoints. |
| MC9S12XDQ256 | Has three 24-bit hardware breakpoints. |
| MC9S12XDQT56, 512 | Has three 24-bit hardware breakpoints. |
| MC9S12XEP100 | Has three 24-bit hardware breakpoints. |
| 68HC812A4 RAM | No hardware breakpoint, no Flash. Code must be in RAM. Tested on Axiom CMD12A4, Elektronikladen HC12compact, Technological Arts Adapt-812DX |
| 68HC912B32 | Has two 16-bit hardware breakpoints. Tested on Axiom CME12B32 |
| 68HC912D60/D60A | Has two 16-bit hardware breakpoints. |
| 68HC912DG128/DG128A | Has two 16-bit hardware breakpoints. Caution is advised if paging is used,
as breakpoints are 16-bits only. Tested on Elektronikladen Card12. |
| 68HC912DT128/DT128A | Has two 16-bit hardware breakpoints. Caution is advised if paging is used, as breakpoints are 16-bits only. |
In the classic monitor, interrupts for RESET, CLOCK FAIL, COP, ILLEGAL OP-CODE, SWI and XIRQ enter the monitor and report a processor state which names the interrupt. All other interrupts are routed through RAM vectors. These RAM vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.
Note that there are no default handlers or other reporting for interrupts when BDM is used.
With the classic monitor, unique processor states are reported in the title bar for
| 0 | RESET |
| 1 | BREAKPOINT (SWI) |
| 2 | XIRQ (FFF4) |
| 3 | Clock Monitor Fail (FFFC) |
| 4 | COP Fail (FFFA) |
| 5 | Illegal Op-code (FFF8) |
| 6 | IRQ (FFF2) |
| 7 | Real Time Interrupt (FFF0) |
| 8 | Timer Channel 0 (FFEE) |
| 9 | Timer Channel 1 (FFEC) |
| 10 | Timer Channel 2 (FFEA) |
| 11 | Timer Channel 3 (FFE8) |
| 12 | Timer Channel 4 (FFE6) |
| 13 | Timer Channel 5 (FFE4) |
| 14 | Timer Channel 6 (FFE2) |
| 15 | Timer Channel 7 (FFE0) |
| 16 | Timer Overflow (FFDE) |
| 17 | Pulse Accumulator Overflow (FFDC) |
| 18 | Pulse Accumulator Input Edge (FFDA) |
| 19 | SPI (FFD8) |
| 20 | SCI 0 (FFD6) |
| 21 | SCI 1 (FFD4) |
| 22 | ATD (FFD2) |
| 23 | Interrupt FFD0 |
| 24 | Interrupt FFCE |
| 25 | Interrupt FFCC |
| 26 | Interrupt FFCA |
| 27 | Interrupt FFC8 |
| 28 | Interrupt FFC6 |
| 29 | Interrupt FFC4 |
| 30 | Interrupt FFC2 |
| 31 | Interrupt FFC0 |
Other processor state values will be shown numerically. Interrupts 23 through 31 have different meanings in different members of the HC12 family. You can change the default strings for these or any other interrupt by means of the STATETEXT command.
While the single byte instruction SWI is preferred for use as a breakpoint instruction, JSR may be used with appropriate modification of the target monitor. When using BDM, the bgnd instruction is used for breakpoint.
The basic monitor, MONHC12.ASM, is less than 1024 bytes in length, and uses about 256 bytes of RAM. The monitor may be assembled with the AS12 assembler available from Motorola/Freescale's Freeware BBS, or with the Dunfield assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting. No monitor is required when using BDM.
Additional information is available about customizing target monitors