NoICE for the 8051 may be used with
The 8051 has a Harvard architecture with several distinct address spaces: code, data/idata, xdata, SFR, and bit. NoICE for 8051 supports two memory addressing models:
For simplicity, code and xdata memory may be combined into a single 16-bit address space. As the 8051 does not have an instruction to write to code memory, the target monitors use the MOVX instructions to read and write code and xdata memory. In order for MOVX to access code memory, PSEN and RD must be combined via external hardware, or appropriate control of the appropriate chip selects must be provided.
This is a popular model for Single Board Computers which have hex monitors and for some single-chip 8051 devices. Consult your documentation to see how your SBC or chip is configured. The address mapping as seen by NoICE is as follows:
If these restrictions are not acceptable to you, you will need to use multiple addresssSpaces.
In order to support the 8051's multiple address spaces, NoICE uses its memory paging/banking syntax
xx:yyyy
where "xx" denotes the address space or page, and "yyyy" denotes the address within that space or page. When entering an address, there are several options for specifying the address space:
Prior to NoICE version 9.1, the address space had to be specified as a hexadecimal integer. For mnemonic convenience, the values used were usually
These values were built into the standard target monitors, and to several of the symbol processing utilities. However, note that these values have no significance to the 8051 processor: you can use any values you like, so long as the target monitor, the symbol processing utility, and NoICE all use the same values. See 3-byte generic pointers below for a reason why you may wish to use different numeric values to specify memory spaces.
Version 9.1 added the PAGENAME command, which allows the memory space to be displayed and entered by name. For example
code:1234
rather than
C:1234
Numeric values may still be used by those who prefer them.
Many 8051 compilers allow you to define 3-byte "generic pointers" that can point to any address space. Usually, the most significant byte indicates the address space. Unfortunately, each compiler vendor uses their own set of values. The table shows the valuse used by some common compilers.
| Compiler | code | data | xdata | pdata |
|---|---|---|---|---|
| SDCC | 0x80 | 0x40 | 0x00 | 0x60 |
| Keil | 0xFF | 0x00 | 0x01 | 0xFE |
| IAR | 0x80 | 0x01 | 0x00 | - |
| Wickenhäuser | 0x01 | 0x02 | 0x00 | - |
| (default) | 0x0C | 0x00 | 0x0D | - |
NoICE's watch window will display 3-byte pointers as (memory-space):(16-bit address). However, in order to expand the watch and view the pointed-to data, your target monitor must be able to accept the 3-byte pointer value. Thus, in most cases you will want to use the set of memory space values that match your compiler, rather than the default set.
This will require you to configure your target monitor appropriately. The page equates are found near the top of the monitor source file for your convenience.
By default, the NoICE symbol-processing utilities CDB2NOI.EXE (for SDCC), OMF51NOI.EXE (for Keil), MAPNOI.EXE (for Dunfield), and IAR_NOI.EXE (for IAR), all generate the appropriate memory-space information as shown above. If you do not wish to use the defaults, you must also specify the appropriate command line switches to each utility.
Unlike any of the other processors supported by NoICE, the 8051 is not clearly MSB-first or LSB-first. LJMP and LCALL fetch addresses most significant byte first. However, as the 8051 has no instruction which loads or stores 16 bit data, the byte order for data is up to the programmer.
Some C compilers follow the "native" MSB-first order for multi-byte data. However, this can be expensive in terms of code space, since the 8051 cannot decrement its DPTR register. Thus, other C compilers store multi-byte data least significant byte first. In order to WATCH and EDIT such data in the correct byte order, NoICE must be told to change the order. This may be done using the MSBFIRST command.
Registers supported are R0 through R7, A, B, PSW, DPTR, SP, PC, and PG if paged memory is used. In addition, register "RB" denotes the register bank bits of the PSW, and register "IE" the interrupt enable SFR. The master interrupt control bit of the actual IE SFR is cleared upon entry to the monitor, and restored from the IE register when a user program is executed. In order to preserve proper monitor operation, the actual IE SFR should not be changed using NoICE memory or input/output commands. All such changes should be made to the IE register.
NoICE for the 8051 can use the NoICE Serial Protocol communicating with a target monitor.
This monitor must be able to write into code space. This may be done by combining xdata and code into a single "pseudo Von Neumann" memory space, or by hardware that provides some other means to write into code space. For example, the Atmel AT89C51ED2 contains Flash-burner code in ROM that allows the NoICE monitor to write into code memory.
The classic monitor resides and location zero, and thus owns the reset and interrupt vectors. Except for RESET, the monitor routes interrupts through a region of RAM which duplicates low memory. This region is initialized with jumps which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor.
Unique processor states are reported in the NoICE title bar for
| 0 | RESET |
| 1 | BREAKPOINT |
| 2 | IE0 |
| 3 | TF0 |
| 4 | IE1 |
| 5 | TF1 |
| 6 | RI & TI |
| 7 | TF2 & EXF2 |
| 8 | Int 0033 |
| 9 | Int 003B |
| 10 | IADC: A/D Converter |
| 11 | IEX2: External Int 2 |
| 12 | IEX3: External Int 3 |
| 13 | IEX4: External Int 4 |
| 14 | IEX5: External Int 5 |
| 15 | IEX6: External Int 6 |
| 16 | Int 0073 |
| 17 | Wake-up from power-down mode |
| 18 | RI1 & TI1: Serial 1 |
| 19 | CAN Controller |
| 20 | SSC Interface |
| 21 | CTF: Compare Timer Overflow |
| 22 | IEX7: External Int 7 |
| 23 | IEX8: External Int 8 |
Other processor state values will be shown numerically. Note that not all of these interrupts exist on some members of the processor family. You can change the default strings for any interrupt by means of the STATETEXT command.
The 8051 unfortunately has no single-byte op-code suitable for use as a breakpoint instruction. Thus, NoICE uses a three byte "LCALL" (hex 12) instruction. This has the effect that breakpoints cannot be placed more closely than three bytes apart, as the inserted breakpoint instructions would overlap. NoICE will prevent the insertion of a breakpoint which would overlap another.
Since single-step is implemented using breakpoints, there may be instructions, such as short forward or backward branches, which cannot be stepped due to overlapped breakpoints.
Several monitors are provided. Most are about 1K bytes in length, including I/O initialization. The monitors uses 256 bytes or less of RAM, but requires no on-chip RAM other than the current register bank, the original contents of which are saved while in the monitor. The monitors are:
Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Additional information is available about customizing target monitors
Here's what you get
Here's what you don't get
In summary, NoICE simulates instruction execution. It does not simulate a competent and thoughtfull programmer. Just because a program "works" on the simulator is no guarantee that it will work on read hardware.