As of the date of this document, NoICE for Windows supports the following processors:
Motorola/Freescale 68HC12 Family
Motorola/Freescale 68HC08 Family
Motorola/Hitachi 6801/6301/6800
Motorola/Freescale 68HC11 Family
Motorola 6809 and Hitachi 6309
Zilog Z80, Z85C1X, Z180 Family
Rockwell / Western Design Center 6502, 65C02 Family
NoICE for the 6801/6301/6800 uses the NoICE Serial Protocol communicating with a target monitor.
NOTE: The Hitachi 6301/6301 instruction set is a superset of the 6801 instruction set, which in turn is a superset of the 6800 instruction set. This version of NoICE supports all of these and may therefore be used with code for any of these targets. The standard target monitor, MON6801.ASM uses no 6301 instructions, but does use several instructions not present on the 6800 (LDD, STD, PSHX, PULX). Thus, some modifications of the monitor will be required to use it on the 6800. Please contact us if you need assistance.
Registers supported are A, B, D, X, SP, PC, CC, and PG if paged memory is used.
In the standard monitor, interrupts for RESET, SWI and 6301 TRAP enter the monitor and report a processor state which names the interrupt. All other interrupts are routed through RAM vectors. These RAM vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET |
| 1 | BREAKPOINT (SWI) |
| 2 | NMI |
| 3 | IRQ |
| 4 | Input Capture (ICF) |
| 5 | Output Capture (OCF) |
| 6 | Timer Overflow (TOF) |
| 7 | Serial Communications Interface (SCI) |
| 8 | TRAP (6301/6303) |
Other processor state values will be shown numerically.
While the single byte instruction SWI is preferred for use as a breakpoint instruction, JSR may be used with appropriate modification of the target monitor.
The basic monitor, MON6801.ASM, is less than 1024 bytes in length, and uses about 256 bytes of RAM. The monitor may be assembled with the Alfred Arnold assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Additional information is available about customizing target monitors
NoICE for the 68HC11 uses the NoICE Serial Protocol communicating with a target monitor.
Registers supported are A, B, D, X, Y, SP, PC, CC, and PG if paged memory is used.
In the standard monitor, interrupts for RESET, CLOCK FAIL, COP, ILLEGAL OP-CODE, SWI and XIRQ enter the monitor and report a processor state which names the interrupt. All other interrupts are routed through RAM vectors. These RAM vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET |
| 1 | BREAKPOINT (SWI) |
| 2 | XIRQ |
| 3 | Clock Monitor |
| 4 | COP Fail |
| 5 | Illegal Op-code |
| 6 | IRQ |
| 7 | Real Time Clock |
| 8 | Timer Capture 1 |
| 9 | Timer Capture 2 |
| 10 | Timer Capture 3 |
| 11 | Timer Compare 1 |
| 12 | Timer Compare 2 |
| 13 | Timer Compare 3 |
| 14 | Timer Compare 4 |
| 15 | Timer Compare 5 |
| 16 | Timer Overflow |
| 17 | Pulse Accumulator Overflow |
| 18 | Pulse Accumulator Edge |
| 19 | SPI |
| 20 | SCI |
Other processor state values will be shown numerically.
While the single byte instruction SWI is preferred for use as a breakpoint instruction, JSR may be used with appropriate modification of the target monitor.
The basic monitor, MONHC11.ASM, is less than 1024 bytes in length, and uses about 256 bytes of RAM. The monitor may be assembled with the AS11 assembler available from Motorola/Freescale's Freeware BBS, or with the Dunfield assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
The monitor BOTBD-E2.ASM is a modification of MONHC11 to support Marvin Green's Bot Board 2. Consult the monitor source code for further details.
Additional information is available about customizing target monitors
NoICE for the 6809 and 6309 use the NoICE Serial Protocol communicating with a target monitor.
Registers supported on the 6809 are A, B, D, X, Y, U, SP, PC, CC, and PG if paged memory is used.
The 6309 version adds registers V, E, F, W and some bits of MD.
In the standard monitor, interrupts for RESET and SWI enter the monitor and report a processor state which names the interrupt. All other interrupts are routed through RAM vectors. These RAM vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET |
| 1 | BREAKPOINT (SWI) |
| 2 | NMI |
| 3 | IRQ |
| 4 | FIRQ |
| 5 | SWI2 |
| 6 | SWI3 |
Other processor state values will be shown numerically.
While the single byte instruction SWI is preferred for use as a breakpoint instruction, SWI2, SWI3 or JSR may be used with appropriate modification of the target monitor. However, these multi-byte instructions will restrict where you can place breakpoints, so SWI is preferred.
The basic monitor, MON6809.ASM, is less than 1024 bytes in length, and uses about 256 bytes of RAM. The monitor may be assembled with the AS09 assembler available from Motorola/Freescale's Freeware BBS, or with the Dunfield assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Several user-supplied monitors are also included.
Additional information is available about customizing target monitors
NoICE for the Z80/Z180 uses the NoICE Serial Protocol communicating with a target monitor.
In addition to the basic Z80 instruction set, the enhanced instructions for the Z85C1X and Z180 family are supported. Because of this, the disassembler may show instructions which are not compatible with a given target. For example, the IN0 instruction of the Z180 does not exist on the Z80 or Z85C1X. While the instruction will be disassembled, operation of single-step is not guaranteed for instructions not supported by a given target.
Registers supported are A, FL, AF, B, C, D, E, H, L, BC, DE, HL, IX, IY, SP, PC, I, IFF (interrupt enable flip flop), A', FL', AF', B', C', D', E', H', L', BC', DE', HL', and PG if paged memory is used.
Except for RESET and the RST instruction used for breakpoint, the standard monitor routes NMI and RSTnn interrupts through a region of RAM which duplicates low memory. This region is initialized with jumps which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor. If interrupt mode two (vectored) is used, interrupts will be independent of the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET (RST 0) |
| 1 | BREAKPOINT (RST nn) |
| 2 | NMI |
| 3 | RST 8 |
| 4 | RST 10 |
| 5 | RST 18 |
| 6 | RST 20 |
| 7 | RST 28 |
| 8 | RST 30 |
| 9 | RST 38 |
| 10 | TRAP (Z180 only) |
Other processor state values will be shown numerically.
While the single byte instruction RST nn is preferred for use as a breakpoint instruction, a three byte CALL may be used with appropriate modification of the target monitor.
The monitor is less than 1024 bytes in length, including I/O initialization, and uses 256 bytes or less of RAM. The monitor MONZ80.S may be assembled with the Zilog ASM80 assembler formerly shipped with Zilog evaluation boards. The monitor MONZ80.ASM may be assembled with the Alfred Arnold Z80 assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Additional information is available about customizing target monitors
NoICE for the 65(C)02 uses the NoICE Serial Protocol communicating with a target monitor.
Registers supported are A, X, Y, SP, PC, CC, and PG if paged memory is used.
Except for RESET and BRK, interrupts in the standard monitor are routed through RAM vectors. These vectors are initialized to enter the monitor and report a processor state which names the interrupt. If user code changes the contents of a RAM vector, that interrupt will be passed to the user-specified routine without entering the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET |
| 1 | BREAKPOINT (BRK) |
| 2 | NMI |
| 3 | IRQ |
Other processor state values will be shown numerically.
The monitor MON6502.ASM is less than 1024 bytes in length. The monitor uses 256 bytes or less of RAM, but requires no page 0 RAM. It contains only instructions from the basic 6502 set, and may be used on either 6502 or 65(C)02 variants. The monitor has been assembled with the Avocet AVMAC (tm) assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Additional information is available about customizing target monitors
NoICE for the 8096/80196 uses the NoICE Serial Protocol communicating with a target monitor.
NoICE96 supports both the 8096 and the 80196 instruction sets. The monitor contains no 80196-specific instructions, and only a few 80196-specific Special Function Register references. It should be easy to modify it for use on an 8096. However, no testing has been performed on an 8096.
The 80196 contains 256 bytes of directly addressable "Register File". This contains both Special Function Registers and general purpose RAM. Of these, the NoICE register window displays PC, SP, PSW, and PG if paged memory is used. Other locations in the Register File may be added to the register window using the DEFREG command, or placed in the watch window using the WATCH command.
The standard monitor supports horizontal windowing, but does not support vertical windowing. Support for vertical windowing may be added to the monitor by the user, if desired. However, since direct and indirect addressing will access different physical locations when vertical windowing is in use, the user must decide which form of address is to be used when the target "read memory" and "write memory" commands are used. In addition, use of direct addressing would require the use of self-modifying code.
Except for RESET, the standard monitor routes interrupts through a region of RAM which duplicates the layout of memory at address 2000h. This region is initialized with vectors to default handlers which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET |
| 1 | BREAKPOINT |
| 2 | Timer Overflow |
| 3 | A/D Complete |
| 4 | HSI Data Available |
| 5 | High Speed Output |
| 6 | HSI.O |
| 7 | Software Timers |
| 8 | Serial Port |
| 9 | EXTINT |
| 10 | Trap (if not used for breakpoint) |
| 11 | Unimplemented Op-code |
| 12 | TI |
| 13 | RI |
| 14 | 4th entry in HSI FIFO |
| 15 | Timer2 Capture |
| 16 | Timer2 Overflow |
| 17 | EXTINT1 |
| 18 | HSI FIFO Full |
| 19 | NMI |
Other processor state values will be shown numerically. Note that not all of these interrupts exist on all members of the processor family.
The TRAP op-code (hex 0F7) is used as a breakpoint instruction.
The monitor is less than 1200 bytes in length, including I/O initialization. The monitor uses 256 bytes or less of RAM, but requires no on-chip RAM other than scratch registers, the original contents of which are saved while in the monitor. The monitor has been assembled with the Alfred Arnold ASM96 assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Thanks to Gene Pfister for the use of his 80196 target board, and for pointing out a number of errors in the original version of the 80196 monitor.
NoICE for the 8085/8080 uses the NoICE Serial Protocol communicating with a target monitor.
NoICE supports the 8085 instruction set including RIM and SIM. In addition, NoICE supports the well known "undocumented" 8085 instructions. Use of these instructions is at the users discretion.
Since the 8085 is a superset of the 8080, this version of NoICE may be used with the 8080 if appropriate changes are made to the serial monitor.
Registers supported are A, FL, B, C, D, E, H, L, BC, DE, HL, SP, PC, IM (8085 interrupt mask as read by RIM), and PG if paged memory is used.
Except for RESET and the RST instruction used for breakpoint, the standard monitor routes TRAP and RSTnn interrupts through a region of RAM which duplicates low memory. This region is initialized with jumps which enter the monitor and report a processor state which names the interrupt. If user code changes the contents of this region, interrupts may be passed to user-specified routines without entering the monitor. If interrupt mode two (vectored) is used, interrupts will be independent of the monitor.
Unique processor states are reported in the title bar for
| 0 | RESET (RST 0) |
| 1 | BREAKPOINT (RST nn) |
| 2 | RST 1 |
| 3 | RST 2 |
| 4 | RST 3 |
| 5 | RST 4 |
| 6 | RST 5 |
| 7 | RST 6 |
| 8 | RST 7 |
| 9 | RST 5.5 (8085) |
| 10 | RST 6.5 (8085) |
| 11 | RST 7.5 (8085) |
| 12 | TRAP (8085 non-maskable interrupt) |
Other processor state values will be shown numerically.
While the single byte instruction RST nn is preferred for use as a breakpoint instruction, a three byte CALL may be used with appropriate modification of the target monitor.
The monitor is less than 1024 bytes in length, including I/O initialization, and uses 256 bytes or less of RAM. The monitors MON8085.ASM and MON8080.ASM may be assembled with the Alfred Arnold assembler. Other assemblers may be used if the appropriate changes are made to pseudo-ops and source file formatting.
Additional information is available about customizing target monitors
The NoICE monitor runs with interrupts disabled so that the program being debugged "freezes" when the monitor is active. In order to do that, the monitor needs to disable interrupts upon entry from the program being debugged, and restore the interrupt state before returning to the program. Control is passed from the program being debugged to the monitor in several ways:
Unfortunately, there is no way for the monitor to know whether the RST instruction was executed as part of the program being debugged, in which case the interrupt enable state is unchanged, or was given to the processor as part of an interrupt acknowledgement, in which case interrupts have been disabled. Since the occurance of one of these RST instructions basically means "hey - you forgot to handle this," the monitor just uses RIM to determine the current state of interrupt enable.
The 8080 instruction set is a subset of the 8085, so the 8085 disassembler is compatible with 8080 programs that use only documented instructions.
In addition to the issued described above the 8080 adds the complication that it lacks the RIM instruction or any other built-in way to determine whether or not interrupts are enabled. As provided, Mon8080.asm always returns to user programs with interrupts disabled. If your programs don't use interrupts, this is all you need.
The 8080 does have a hardware pin, INTE, which signals whether or not processor interrupts are enabled. If your target hardware provides a way to read the state of this pin, perhaps via an 8259 Interrupt Controller or similar, you can modify the NoICE 8080 monitor to return this state along with the processor registers. NoICE will display it as "IM," and the monitor can use the value to restore the interrupt state when program execution continues. Refer to the 8080 monitor source code, Mon8080.asm, for details.
Additional processors may be supported in the future, as time and interest allow. Some likely candidates are listed below. If you are interested in one of these, or wish to suggest another target, please contact us.
The DOS version of NoICE also supported the 6805, MELPS740, TMS370, and H8/300. A version of NoICE for Windows for any of these processors could be done if there were sufficient interest. Please contact us to lobby for your favorite.
I would like to support the Microchip PIC and the Atmel AVR, but the architecture of both pretty much precludes the use of a monitor-based debugger. For the PIC in particular: code memory is wider than 8 bits, some members of the family have very shallow stacks, and there is no way to push or pull data from the stack except for call and return. If you can think of a way around these problems, please contact us.